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W65C832PXB Key Features

65xx ASIC or FPGA Controller Development

  • Lattice ECP2M−50 FPGA with 48 kLUTs, 4147 kbit of Embedded Block RAM, 22 sysDSP™ blocks, 88 18×18 multipliers,10 PLLs, and 270 user I/O pins
  • Lattice MachXO™ with 640 LUTs and 6.1 Kbit of RAM

Connectivity

  • USB 2.0 connector and integrated ispDOWNLOAD® cable for JTAG programming the FPGA
  • Flywire connector for programming using an ispDOWNLOAD cable (available separately from Lattice)
  • USB 2.0 compatible host connectors for interfacing with WDC’s ProSDK Development Tools
  • SATA interface with two LVDS signal pairs for high-speed data transfer
  • Altera Santa Cruz compliant connectors (2 x 40) providing 46 lines of I/O Expansion

Expansion/Debug and Programming

  • 100−pin “MESA” connector compliant with T&MT USB PHY Standards
  • 28−pin expansion header for I/O. Compatible with WDC’s Parallel IO Board
  • LCD connector for character displays, with contrast potentiometer
  • 38−pin MICTOR connector for high speed Logic Analyzer connection
  • 25 MHz oscillator with clock distribution buffer
  • 4−pin DIP half socket for user selected oscillator
  • One HEX Rotary Switch
  • Dual Character 7−segment Display
  • 8 Activity LEDs
  • 8 Test Points
  • 4 Pushbutton switches for debug and user input
  • Green LED to indicate the proper operation of the 3.3V and 2.5 V power supplies
  • Blue LED which shows the configuration status (“DONE”)
  • Red LED to signal that the FPGA can be configured (“INIT”)
  • Yellow LED indicating the FPGA PROGRAM# I/O is asserted (“PROGRAM#”)
  • Program key to initiate the configuration sequence of the FPGA from SPI Flash memory
  • Reset key

Power

  • 5V power supply
  • Switching regulator for the generation of the 3.3V I/O voltage and the 1.2Vcore voltage
  • Robust power configuration with jumper selections to power board with either of the two USB ports or the DC input jack

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