WDC Development Platform:
MyMENSCH™ Microcomputer is the Western Design Center’s VASIC-to-ASIC™ (SBC), using a Programmable logic System on a Chip (PSoC) Intel PSG MAX10 10M08 FPGA.
Virtual ASIC (VASIC™) is a softcore microprocessor version of WDC’s 65xx Microprocessor family of GDSII design(s) that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic (e.g.FPGA)
VASIC vs. ASIC Design Advantages
|VASIC FPGA Design|
|Faster time-to-market||No layout, masks or other manufacturing steps are needed|
|No upfront non-recurring expenses (NRE)||Costs typically associated with an ASIC design|
|Simpler design cycle||Due to software that handles much of the routing, placement, and timing|
|More predictable project cycle||Due to elimination of potential re-spins, wafer capacities, etc.|
|Field reprogramability||A new bitstream can be uploaded remotely|
|Full custom capability||For design since device is manufactured to design specs|
|Lower unit costs||For very high volume designs|
|Smaller form factor||Since device is manufactured to design specs|
VASIC vs. ASIC Design Flow
The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis, and mask / re-spin stages of the project since the design logic is already synthesized to be placed onto an already verified, characterized FPGA device. However, when needed, WDC provides the advanced floorplanning, hierarchical design, and timing to allow users to maximize performance for the most demanding designs.
Design Flow Outline:
- Architecture design. This stage involves analysis of the project requirements, problem decomposition and functional simulation (if applicable). The output of this stage is a document which describes the future device architecture, structural blocks, their functions and interfaces.
- HDL design entry. The device is described in a formal hardware description language (HDL). The most common HDLs are VHDL and Verilog.
- Test environment design. This stage involves writing of test environments and behavioral models (when applicable). They are later used to ensure that the HDL description of a device is correct.
- Behavioral simulation. This is an important stage that checks HDL correctness by comparing outputs of the HDL model and the behavioral model (being put in the same conditions).
- Synthesis. This stage involves conversion of an HDL description to a so-called netlist which is basically a formally written digital circuit schematic. Synthesis is performed by a special software called synthesizer. For an HDL code that is correctly written and simulated, synthesis shouldn’t be any problem. However, synthesis can reveal some problems and potential errors that can’t be found using behavioral simulation, so, an FPGA engineer should pay attention to warnings produced by the synthesizer.
- Implementation. A synthesizer-generated netlist is mapped onto particular device’s internal structure. The main phase of the implementation stage is place and route or layout, which allocates FPGA resources (such as logic cells and connection wires). Then these configuration data are written to a special file by a program called bitstream generator.
- Timing analysis. During the timing analysis special software checks whether the implemented design satisfies timing constraints (such as clock frequency) specified by the user.