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Educational IP License

Introduction

WDC has proudly supported educational institutions and continues to do so. In 2005, WDC supported the Introduction to VLSI Design with System on Chip Design Reuse: A Tutorial for Students. This tutorial was created in the absence of a VLSI course that Bill Mensch taught at ASU East. The tutorial focused on the W65C122S, a GDSII based microcontroller featuring the W65C02, W65C22, RAM, and ROM. The design from this tutorial was taped out once through Tanner Research, however, the steps for tapeout are not covered in the tutorial. WDC continues to support professors and students of VLSI design, by offering chips, boards, and IP for student use at and within university Colleges of Engineering.

Many universities worldwide still teach VLSI design, however, there are still many that either never had a course, dropped the course after the teaching professor left, or the course is lacking the inclusion of an option to tape out and evaluate a completed chip.

WDC has been working with Dr. Yiyan Li to provide IP, boards, and support for a VLSI course that Dr. Li is creating at Fort Lewis College. This course will tape out a design on the TSMC 180nm technology. WDC has designed the W65C02SOC-40 microcontroller for use in Dr. Li’s course, and we feel that this same solution can be used in courses worldwide. We feel that using this design, professors can create a course that brings more value to their students and institutions. Students and professors will be able to work with their own EDA tool design flow in addition to WDC’s tool design flow, software development tools, and technology. In addition, WDC is partnering with Cadence (EDA design tools), TSMC (wafer foundry), and Muse Semiconductor (MPW services) for a complete tapeout of a SOC.

The W65C02SOC-40 is an 8–bit microcontroller with WDC’s W65C02S CPU, VIA, ACIA, IP along with open source I2C, SPI modules. In support of the IP, WDC has the MyMENSCH Rev-C board for emulation, the W65C02SOC-40EDU board for adding modules to MyMENSCH, and the W65C02SOC-40TEB for the testing and evaluation of the SOC device that is created during the course. The W65C02SOC-40 datasheet contains information about the microcontroller, the EDU board, and the TEB board.

W65C02SOC-40

W65C02SOC-40 DataSheet   MyMENSCH Rev-C Information

Key Features of the W65C02SOC-40 Microcontroller

  • IO Operating Voltage – 3.3V
  • Core Operating Voltage – 1.8V
  • System Operation Speed – Determined by the chosen Oscillator
  • W65C02RTL MPU
  • W65C22RTL VIA
  • W65C51RTL ACIA (x2) – XTLI @ 1.8432 MHz
  • W65CGPIO ports (8 pins per port) (x4 ports)
  • SPI Primary
  • I2C Primary
  • WDC 2K byte Monitor for boot loading and debugging code
  • 16K bytes User code SRAM boot loaded from USB or copied from external SPI serial FLASH memory
  • 16K bytes for for data SRAM
  • JTAG available on MyMENSCH™

W65C02SOL-28

W65C02SOL28 DataSheet   MyMENSCH Rev-C Information

Key Features of the W65C02SOL-28 Microcontroller

  • Operating Voltage – TBD
  • System Operation Speed – Determined by the chosen Oscillator
  • W65C02RTL MPU
  • W65C22RTL VIA
  • 1kb (128 Bytes) User code space Hard Mask Programable at MT2
  • 512b (64 Bytes) of SRAM in Page 0/1

Example Syllabus for VLSI Course

  1. The System on Chip (SoC) Project – Project Overview and Introduction to 65xx Technology and Tools
  2. Simulator/SBC/FPGA Projects
  3. Projects Continued
  4. Cadence VLSI Design tools and Design Entry of SoC defined features in Cadence
  5. Creation and design entry of custom SoC features in Cadence
  6. Custom SoC features continued
  7. Verilog simulation using Verilog – XL and NC_Verilog in Cadence.
  8. Simulation Continued
  9. Emulating the SoC in FPGA using Intel Quartus tools and WDCTools.
  10. Emulating Continued
  11. Verilog Synthesis using the Cadence RTL Compiler / SoC Encounter Place and Route.
  12. Place and Route Continued with Timing Closure
  13. The pad frame, GDSII and Chip assembly.
  14. Tape out verification of the SoC / Post place and route simulation.
  15. Review of the manufacturing flow for the completed SoC and release to Muse Semiconductor.
  16. Receive SoC approval from Muse/TSMC and make preparations for the test and evaluation in the following Fall Semester of the SoC in the Test and Evaluation Board (TEB).

The course roadmap defines a learning experience that will provide students with real-world VLSI experience. It also takes into consideration the seven student learning outcomes that are part of ABET accreditation (1. Solve problems; 2. Design; 3. Communicate [writing and oral]; 4. Ethics and economics; 5. Teamwork; 6. Experimentation; 7. Life-long learning [acquire new knowledge]).

I’m interested, what are the next steps?

1.) Download, review, and sign WDC’s standard NDA. (Download below)
2.) Once NDA is in place, WDC will provide Technology License Agreement (TLA).
3.) Professor and/or student must have an NDA with Muse Semiconductor for tapeout services through TSMC.

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