WDC provides the following Data Deliverables in our technology transfer.

	Hard Core
	GDSII Mask Files GDSII Schematic Files GDSII Hard Core Flowchart Spice Extracted Netlist CDL Netlist for LVS Mask ROM files N/A Verilog Structural Gate Netlist
	Viewlogic Files
	Viewlogic Standard Product Behavioral Model Footprint Viewlogic Behavioral Core Footprint Viewlogic Standard Product Gate Model Footprint Viewlogic Buffer Ring Viewlogic Gate Core Footprint
	Soft Core
	Verilog RTL Model
	Firm Core
	Xilinx Synthesized Gate Model
	Common Files
	Verilog Test files Sentry Test files

N/A – Not Applicable
NP – Not Planned
UC – Under Construction

The W65C02 Hard Core is a manually optimized full custom hard core that has been used in billions of applications.
The W65C02 Hard Core has been manufactured in 3um, 2um, 1.5um, 1.2um, 0.8um, 0.6um, 0.5um and 0.35um technology.

WDC’s microprocessor IP has been tailored for ease of reuse. The hard core IP is in the industry standard GDSII format.The buffer ring has been designed with off-chip drivers, including latch-up and ESD protection. When the core is embedded,the off-chip buffer ring is replaced with On-Chip-Bus (OCB) interface ring. The abstract cell is the connecting points with labels that provide core verification and system verification. WDC’s test programs require that all test pins be compared to the standard test vendors.

W65C02 Soft Core (RTL model)

The W65C02 Soft Core is a RTL (Register Transfer Level) description in Verilog HDL (Hardware Description Language).  This single clock logic architecture is technology independent.  WDC’s W65C02 Soft Core is designed to replace the industry standard W65C02 8-bit microprocessor and can be used as a drop-in replacement in ASIC’s.

FPGA Implementation Results

Implementation Results for the W65C816S in the LatticeXP Device

The following are typical performance and utilization results.

W65C02 Xilinx Firm Core

The W65C02 Firm Core is available as a synthesized version of the Soft Core for Xilinx FPGA’s. It is verified on silicon and tested with the industry standard production test vectors and an in-system verification. The FPGA device used for the Firm Core verification is the XC4085XL Xilinx part. The synthesis tool used is Leonardo Spectrum from Mentor for FPGA or standard cell library synthesis. The W65C02 Xilinx Firm Core is based on the W65C02 industry standard and tested on silicon (XC4085 series) with the original test vectors of the Hard Core. The synthesis is done with Mentor Leonardo Spectrum software. It uses 899 Logic Blocks. An interface board for the 559 pin Xilinx FPGA for WDC’s Developer Boards and 40 pin DIP standard product is available as well.