W65C02SOL-28 Features and Specification
Key Features of the W65C02SOL-28 Microcontroller
- Operating Voltage – TBD
- System Operation Speed – Determined by the chosen Oscillator
- W65C02RTL MPU
- W65C22RTL VIA
- 1kb (128 Bytes) User code space Hard Mask Programmable at MT2
- 512b (64 Bytes) of SRAM in Page 0/1
Example Syllabus for a VLSI Course
- The System on Chip (SoL) Project – Project Overview and Introduction to 65xx Technology and Tools
- Simulator/SBC/FPGA Projects
- Projects Continued
- Cadence VLSI Design tools and Design Entry features in Cadence
- Creation and design entry of custom SoL features in Cadence
- Custom SoL features continued
- Verilog simulation using Verilog – XL, and NC_Verilog in Cadence.
- Simulation Continued
- Emulating the SoL in FPGA using Intel Quartus tools and WDCTools.
- Emulating Continued
- Verilog Synthesis using the Cadence RTL Compiler / Encounter Place and Route.
- Place and Route Continued with Timing Closure
- The pad frame, GDSII, and Chip assembly.
- Tape out verification of the SoL / Post place and route simulation.
- Review of the manufacturing flow for the completed SoL and release to PragmatIC Semiconductor.
- Receive approval from PragmatICand make preparations for the test and evaluation in the following Fall Semester of the Test and Evaluation Board (TEB).
The course roadmap defines a learning experience that will provide students with real-world VLSI experience. It also takes into consideration the seven student learning outcomes that are part of ABET accreditation (1. Solve problems; 2. Design; 3. Communicate [writing and oral]; 4. Ethics and economics; 5. Teamwork; 6. Experimentation; 7. Life-long learning [acquire new knowledge]).
I’m interested, what are the next steps?
Please Contact Us if you are a professor at a College or University and are interested in integrating our IP into your existing or new course offering.
Note that each Educational institution must have an NDA with PragmatIC Semiconductor prior to licensing WDC IP and tapeout a design.