WDC IP Design Flow and Process

WDC 65xx Technology is proven in many markets. Here is some information on our design flow and processes.

WDC ASIC Design Flow  WDC FPGA Design Flow

 W65C02-LFE2M50-1

W65C02-LFE2M50-1 DataSheet  Developer Qualification Form  WDC Licensing Informtion

The W65C02-LFE2M50-1 is a minimal System on Programmable Chip example based on WDC’s Verilog IP Cores. This micro-computer uses the W65C02SRTL as the processor and provides the user with a complete kit to begin application development and familiarization with the 65xx technology family. This micro-computer is targeted for WDC’s W65C832PXB which features the Lattice ECP2M50 FPGA. The PMCU has an embedded monitor located in ROM that provides a debug interface to WDCTools.

W65C816-LFE2M50-1

W65C816-LFE2M50-1DataSheet  Developer Qualification Form  WDC Licensing Informtion

The W65C816-LFE2M50-1 is a minimal System on Programmable Chip example based on WDC’s Verilog IP Cores. This micro-computer uses the W65C816SRTL as the processor and provides the user with a complete kit to begin application development and familiarization with the 65xx technology family. This micro-computer is targeted for WDC’s W65C832PXB which features the Lattice ECP2M50 FPGA. The PMCU has an embedded monitor located in ROM that provides a debug interface to WDCTools.

KEY FEATURES OF THE 65xx PMCUs

• Microprocessor Core
• 32K x 8 FlashROM on chip
• 32K x 8 SRAM on chip

• General Purpose IO modules (2 used for Parallel GPIO connector, 2 for USB TIDE PortInterface, 1 for LEDs Interface, 2 for Dual 7-Segment LED, 1 for User pushbuttons and HEX Input)

• Programmable Hardware Breakpoint for added in-circuit debug
• WDCTools for Assembly and ANSI/ISO Standard C application development