Patents By Inventor William D. Mensch, Jr.

• Co Inventor– U.S. Patent Number 20170039135

Flash memory is nonvolatile computer storage that can be electrically erased and reprogrammed. In general, flash memory has a high resistance to mechanical shock, small foot print,relatively fast read times that are comparable to dynamic Random Access Memory (RAM), is energy efficient and can store data for years without power. Flash memory is used in a variety of applications, including personal computers, mobile devices, digital cameras, video games, scientific instrumentation, industrial robots, medical electronics and other devices.

• U.S. Patent Number 6,052,792
  The invention relates to a system for (1) speed control circuitry allowing the microprocessor access to both fast and slow memories and I/O interface to effectuate automatic reduction of overall system power and (2) determining program execution location.
• U.S. Patent Number 5,737,613
  The invention relates to an efficient topography for a CMOS microcomputer including a sixteen bit static low power CMOS microprocessor, 8192 bytes of ROM, 576 bytes of RAM, eight chip select outputs, eight 16 bit timers with maskable interrupts, four UARTs, 29 priority encoded interrupts, built in de-bug features, a bus control register for external memory bus control, interface circuitry for I/O devices, time of day clock features, twin tone generators, a bus control register for external memory bus control, an abort input for low cost virtual memory interface, a high performance interrupt driven parallel bus interface, and system speed control circuitry to allow the microprocessor access to both slow and fast memories and I/O interface and to effectuate automatic reduction of overall system power.
• U.S. Patent Number 5,511,209
  The invention relates to a system for effectuating switching of a CMOS integrated circuit microprocessor from high speed, high power operation to low speed, low power operation, and vise versa, in response to a clock selection signal.
• U.S. Patent Number 5,438,681
  The invention relates to an efficient topography for a CMOS microcomputer including a sixteen bit static low power CMOS microprocessor, 8192 bytes of ROM, 576 bytes of RAM, eight chip select outputs, eight 16 bit timers with maskable interrupts, four UARTs, 29 priority encoded interrupts, built in de-bug features, a bus control register for external memory bus control, interface circuitry for I/O devices, time of day clock features, twin tone generators, a bus control register for external memory bus control, an abort input for low cost virtual memory interface, a high performance interrupt driven parallel bus interface, and system speed control circuitry to allow the microprocessor access to both slow and fast memories and I/O interface and to effectuate automatic reduction of overall system power.
• U.S. Patent Number 5,212,800
  The invention relates to a system for operating a CMOS integrated circuit microcomputer to detect trinary logic states without using trinary logic levels. Microprocessors do not ordinarily contain additional components that are needed in a microcomputer system, such as a read only memory for storing programs, a random access memory for storing variables and data, timers, UART’s, I/O functions, priority interrupt systems and the like. However, with the wide availability and commercial success of quite a number of microprocessors, various suppliers have begun using commercially available microprocessor designs as the “cores” of larger microcontrollers or microcomputers on single silicon chips that include not only the microprocessor, but some or all of the above-mentioned components and others.
• U.S. Patent Number 5,123,107
  The invention relates to an efficient topography for a CMOS microcomputer including an eight bit CMOS microprocessor, 4096 bytes of ROM, 192 bytes of RAM, eight chip select outputs, two 16 bit timers, a serial interface bus circuit configured for connection to a token passing local area network, a UART, a watchdog timer with restart interrupt capability, 22 priority encoded interrupts, a toolbox emulation interface, real time clock features, a bus control register for external memory bus control, and interface circuitry for I/O devices.
• U.S. Patent Number 5,097,413
  The invention relates to an efficient topography for a sixteen bit CMOS microprocessor chip having the capability of either operating as a sixteen bit microprocessor or operating to emulate the well-known 6502 eight bit integrated circuit microprocessor, depending only on the state of a software “emulation bit” or “E” bit.
• U.S. Patent Number 4,876,639
  The invention relates to an efficient topography for a sixteen bit CMOS microprocessor chip having the capability of either operating as a sixteen bit microprocessor or operating to emulate the well-known 6502 eight bit integrated circuit microprocessor, depending only on the state of a software “emulation bit” or “E” bit.
• U.S. Patent Number 4,800,487
  The invention relates to topography for integrated circuit microprocessor chips.
• U.S. Patent Number 4,739,475
  The invention relates to an efficient topography for a sixteen bit CMOS microprocessor chip having the capability of either operating as a sixteen bit microprocessor or operating to emulate the well-known 6502 eight bit integrated circuit microprocessor, depending only on the state of a software “emulation bit” or “E” bit.
• U.S. Patent Number 4,652,992
  The invention relates to topography for integrated circuit microprocessor chips.
• U.S. Patent Number 4,263,650
  This invention is related to the following patent applications filed simultaneously with the parent application of the present application and assigned to the assignee of this application: Ser. No. 519,150, now abandoned, by Bennett et al
• U.S. Patent Number 4,218,740
  This invention is related to the following patent applications filed simultaneously herewith and assigned to the assignee of this application: Ser. No. 519,150, now abandoned, by Bennett et al, entitled MICROPROCESSOR ARCHITECTURE
• U.S. Patent Number 4,099,232
  The invention is in the field of interval timers, as for microprocessor systems, for example, the microprocessor system sold by MOS Technology, Inc., of Pennsylvania under the generic designation 650X.
• U.S. Patent Number 4,087,855
  This invention is related to the following patent applications filed simultaneously herewith and assigned to the assignee of this application: Ser. No. 519,150, by Bennett et al. entitled MICROPROCESSOR ARCHITECTURE;ed
• U.S. Patent Number 4,086,627
  This invention is related to the following patent applications filed simultaneously herewith and assigned to the assignee of this application: Ser. No. 519,150, by Bennett et al entitled MICROPROCESSOR ARCHITECTURE; Ser. No. 519,138,
• U.S. Patent Number 4,020,472
  An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system.
• U.S. Patent Number 3,991,307
  Disclosed is an integrated circuit microprocessor with a parallel binary adder whose output can be corrected on-the-fly to provide decimal results.
• U.S. Patent Number 3,968,478
  The chip architecture of an MOS peripheral interface adapter chip includes data bus buffers arranged along one edge of the chip, peripheral interface buffers.