The following is a list of foundational modules which WDC has proven to start the VASIC-to-ASIC™ process. In addition to these items third party licensed cores and IP can be integrated dependent on the FPGA model identified and any system requirements identified by you or your end customer.
W65C02 (RTL model)
The W65C02 Soft Core is a RTL (Register Transfer Level) description in Verilog HDL (Hardware Description Language). This single clock logic architecture is technology independent. WDC’s W65C02 Soft Core is designed to replace the industry standard W65C02 8-bit microprocessor and can be used as a drop-in replacement in ASIC’s.
W65C816 (RTL model)
The W65C816 Soft Core is a RTL (Register Transfer Level) description in Verilog HDL (Hardware Description Language) and is a synthesizable model. This single clock logic architecture is technology independent. WDC’s W65C816 Soft Core is designed to replace the industry standard W65C816 16-bit microprocessor and can be used as a drop-in replacement is ASIC’s. he behavioral model is equivalent to the original W65C816 hard core. The standard chip model includes the softcore and the buffer ring in RTL code. If a minimum amount of gates are needed, the hard core of the W65C816C should be used.
W65C22 (RTL model)
8/16-bit Versatile Interface Adapter (VIA) is a flexible I/O device . In addition to I/O, the it provides two programmable 16-bit Interval Timer/Counters with latches and synchronous serial interface shift registers.
W65C51 (RTL model)
The Asynchronous Communications Interface Adapter (ACIA) provides easily implemented, program controlled interface between microprocessor based systems and serial communications data sets and modules.
Custom designed General Perpose Input/Output (GPIO) with programmable edge interrupts, and pull up resistors
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.
Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola’s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. Enhancements to the original interface include a wider supported operating frequency range, 4 entries deep read and write FIFOs, and programmable transfer count dependent interrupt generation. The high compatibility with the M68HC11 SPI port ensures that existing software can use this core without major modifications. New software can use existing examples as a starting point. The core features an 8 bit wishbone interface.
Hardware Breakpoint Module (HBM)
The Hardware Breakpoint Module pulls NMIB low during a match condition. HBM addresses 00, 01 are for the low and high byte of 16-bit address bus matching registers. HBM addresses 02, 03 are RESERVED for future 32 bit address bus matching registers. HBM address 04 is the data bus matching register. HBM addresses 05, 06, 07 are RESERVED for future 32-bit data bus matching registers. HBM addresses 08-0E are RESERVED for future use. HBM address 0F is the HBM Control Register. The monitor needs to write a “0” into the Control Register after a breakpoint has been read to clear it. Writing a “1” to Bit 7 will cause a manual NMI if the breakpoint is enabled.