Introduction:
FPGA? ASIC? Microprocessor? Microcontroller? What is the best choice for your project? This blog post from Element 14 is loaded with information comparing FPGA, ASIC, Microcontrollers, and Microprocessors. Digilent has an excellent article explaining the advantages of FPGAs and microcontrollers. It shows that when you combine the two, you can make an even more powerful solution.
IoT White Papers
WDC’s FPGA Microcontrollers are general purpose for any industry, but have features that make them a perfect fit for IoT and next-generation industrial controls applications. The following are a few white papers for applications areas that we see as great matches for our FPGA Microcontroller technology.
IoT (from the World Economic Forum)
Advanced Metering Infrastructure (AMI)
Standard FPGA Microcontrollers:
WDC uses Intel’s MAX10 FPGA Family of FPGAs for it’s FPGA Microcontroller products. The MAX10 has unique features such as 12-bit Analog-to-Digital converter, Hardware Multipliers, User FLASH Memory, and a 64-bit Unique Chip ID for enabling added security. These features packed into a low-cost FPGA set the MAX10 apart from its competitors. By combining the MAX10 FPGA, WDC’s microprocessor and peripheral IP, and other IP as needed WDC gives you a best-of-all-worlds microcontroller solution. The button below shows the modules used in WDC’s FPGA Microcontrollers.
Supported Modules
Custom FPGA Microcontrollers:
WDC offers flexibility for your commercial product by offering Microcontrollers tailored for your specific need. We can start with our Standard FPGA Microcontroller, add or remove our standard modules, integrate Third Party IP, and even develop custom IP as required.
FPGA vs. ASIC Design Advantage
| FPGA Design | |
|---|---|
| Advantage | Benefit |
| Faster time-to-market | No layout, masks or other manufacturing steps are needed |
| No upfront non-recurring expenses (NRE) | Costs typically associated with an ASIC design |
| Simpler design cycle | Due to software that handles much of the routing, placement, and timing |
| More predictable project cycle | Due to elimination of potential re-spins, wafer capacities, etc. |
| Field reprogramability | A new bitstream can be uploaded remotely |
| ASIC Design | |
|---|---|
| Advantage | Benefit |
| Full custom capability | For design since device is manufactured to design specs |
| Lower power consumption | Ideal for battery operated designs |
| Higher speeds | 10x+ higher system clock frequencies |
| More Memory | 10x+ memory capacity while maintain lower die costs |
| Lower unit costs | For very high volume designs |
| Smaller form factor | Since device is manufactured to design specs |
FPGA-to-ASIC Conversion:
For applications that require it, WDC’s FPGA Microcontroller designs can be converted to an ASIC. WDC has a long-term relationship with Progate Group Corporation (PGC) for ASIC manufacturing, testing, and even FPGA-to-ASIC conversion.
Where To Buy IC Package Types IC Cross Reference Single Board Computers WDCTools Downloads Programming Manual
FPGA Microcontrollers
W65C02SOC40
The W65C02SOC40 is the 8–bit microcontroller featured in MyMENSCH Rev-C. This is available in build form and IP form as part of WDC’s 6502 Educational IP.
The FPGA build on MyMENSCH Rev-C is meant to be a prototyping platform that can be targeted to an ASIC/SoC Multi-Project Wafer tapeout.
DataSheet MyMENSCH Rev-C Programming Manual WDCMON v2.0 Manual
Features of the W65C02SOC40 FPGA Microcontroller.
- Intel PSG MAX10M08SA FPGA with ~8,000 Logic Elements Available
- Operating Voltage – 3.3V
- System Operation Speed – 14.7456 MHz on MyMENSCH Rev C
- W65C02RTL MPU
- W65C22RTL VIA
- W65C51RTL ACIA (x2) – XTLI @ 1.8432 MHz
- W65CGPIO E Port (Used for ACIA_A Handshake, SPI CS, and UART CS)
- SPI Primary
- I2C Primary
- WDC 2K byte Monitor for boot loading and debugging code
- 8K bytes User code SRAM boot loaded from USB
- 8K bytes for data SRAM
- JTAG available on MyMENSCH™
W65C02SOC64
The W65C02SOC64 is the 8–bit microcontroller featured in MyMENSCH Rev-C and builds on the concepts behind the W65C02SOC40, adding the ability for students to add their own “micromodules”. WDC’s micromodule example is adding the W65C22SRTL and GPIOA to the base controller design. This is available in build form and IP form as part of WDC’s 6502 Educational IP. The FPGA build on MyMENSCH Rev-C is meant to be a prototyping platform that can be targeted to an ASIC/SoC Multi-Project Wafer tapeout. WDC is planning a tapeout using the SkyWater 130nm process through EFabless and packaged in a QFN64 package.
DataSheet MyMENSCH Rev-C Programming Manual WDCMON v2.0 Manual
Features of the W65C02SOC64 FPGA Microcontroller.
Base Microcontroller Features
- Intel PSG MAX10M08SA FPGA with ~8,000 Logic Elements Available
- IO Operating Voltage – 3.3V
- Core Operating Voltage – 1.8V
- System Operation Speed – 14.7456 MHz
- W65C02RTL MPU
- W65C51RTL ACIA (x2) – XTLI @ 1.8432 MHz Created with divider logic from XCLK
- W65CGPIO E Port (Used for ACIA_A Handshake, SPI CS, and UART CS)
- SPI Primary
- I2C Primary
- WDC 2K byte Monitor for boot loading and debugging code
- 8K bytes User code SRAM boot loaded from USB
- 8K bytes of data SRAM
MicroModule Features (28 MMIO Pins Available for all custom microcontrollers)
- W65C22RTL VIA (Uses 20 MMIO Pins)
- W65CGPIO Port A (Uses 8 MMIO Pins)
W65C02i1M08SA
The W65C02i1M08SA is the 8–bit microcontroller featured in MyMENSCH Rev-C.
DataSheet MyMENSCH Rev-C Programming Manual Supported Modules
Features of the W65C02i1M08SA
- Intel PSG MAX10M08SA FPGA with 8,000 Logic Elements Available
- Operating Voltage – 3.3V
- W65C02RTL MPU @ 14.7456 MHz with external memory bus for memory and module expansion
- W65C22RTL VIA (x2)
- W65C51RTL ACIA (x3) – ACIA XTLI Operation Speed – 1.8432 MHz
- W65CGPIO 5 register and 2 register
- De-bounced Keypad GPIO_A
- W65CHBM Hardware Breakpoint Module
- SPI Master
- I2C Master
- WDC 2K byte for 2048 bytes of CFM MyMENSCH™ Monitor for boot loading and debugging code
- 30K bytes for a total of 30,720 bytes for User code SRAM boot loaded from USB or copied from UFM
- 12K bytes for a total of 12,288 bytes for data SRAM
- JTAG available on MyMENSCH™ Rev-A on J4
- 16×16 Hardware multiplier (x2 – Signed and Unsigned)
- 32K bytes for a total of 32,768 bytes of User FLASH Memory (UFM)
- 64-bit Unique Chip ID/serial number programmed in the Intel MAX10 factory
- 18,446,744,073,709,551,616 Unique IDs
W65C165i1M08SA
The W65C165i1M08SA is the 8–bit microcontroller featured in MyMENSCH Rev-C.
DataSheet MyMENSCH Rev-C Programming Manual Supported Modules
Features of the W65C165i1M08SA
- Intel PSG MAX10M08SA FPGA with 8,000 Logic Elements Available
- Operating Voltage – 3.3V
- W65C02RTL MPU @ 14.7456 MHz
- W65C22RTL VIA (x3)
- W65C51RTL ACIA (x2) – ACIA XTLI Operation Speed – 1.8432 MHz
- W65CGPIO 5 register and 2 register
- De-bounced Keypad GPIO_A
- W65CHBM Hardware Breakpoint Module
- SPI Master
- I2C Master
- WDC 2K byte for 2048 bytes of CFM MyMENSCH™ Monitor for boot loading and debugging code
- 2K bytes 2048 bytes reserved for ADC
- 30K bytes for a total of 30,720 bytes for User code SRAM boot loaded from USB or copied from UFM
- 10K bytes for a total of 10240 bytes for data SRAM
- JTAG available on MyMENSCH™ Rev-A on J4
- 16×16 Hardware multiplier (x2 – Signed and Unsigned)
- 12-bit ADC (1x), 1 dedicated pin, 8 dual-function (digital IO or ADC) pins, Temperature Sense Diode
- 172K bytes for a total of 176,128 bytes of User FLASH Memory (UFM)
- 64-bit Unique Chip ID/serial number programmed in the Intel MAX10 factory
- 18,446,744,073,709,551,616 Unique IDs
W65C816i1M16SA
The W65C816i1M16SA is the 8/16–bit microcontroller featured in MyMENSCH Rev-B.
DataSheet MyMENSCH Rev-B Programming Manual Supported Modules
Features of the W65C816i1M16SA
- Intel PSG MAX10M16SA FPGA with 16,000 Logic Elements Available
- Operating Voltage – 3.3V
- W65C816RTL MPU @ 14.7456 MHz with external memory bus for expanding memory and peripheral modules
- W65C22RTL VIA (x2)
- W65C51RTL ACIA (x2) – ACIA XTLI Operation Speed – 1.8432 MHz
- W65CGPIO 5 register and 2 register
- De-bounced Keypad GPIO_A
- W65CHBM Hardware Breakpoint Module
- SPI Master
- I2C Master
- WDC 2K byte for 2048 bytes of CFM MyMENSCH™ Monitor for boot loading and debugging code
- 2K bytes 2048 bytes reserved for ADC
- 30K bytes for a total of 30,720 bytes for User code SRAM boot loaded from USB or copied from UFM
- 29K bytes for a total of 29,696 bytes for data SRAM
- 16×16 Hardware multiplier (x2 – Signed and Unsigned)
- 32/32-bit Hardware Divider
- 12-bit ADC (1x), 1 dedicated pin, 8 dual-function (digital IO or ADC) pins, Temperature Sense Diode
- 296K bytes for 303,104 bytes of User FLASH Memory (UFM)
- 64-bit Unique Chip ID/serial number programmed in the Intel MAX10 factory
- 18,446,744,073,709,551,616 Unique IDs