Home » FPGA Design Flow Overview

FPGA Design Flow Overview

WDC Development Platform:


Features    Block Diagram    Intel FPGA Development Tools

MyMENSCH™ Development Platform is the Western Design Center’s FPGA-to-ASIC™ (SBC), using a Programmable logic System on a Chip (PSoC) Intel PSG MAX10 10M08 FPGA.

The MyMENSCH™ Development Platform is built with technology from the most trusted name in the industry and leader in 65xx technology in conjunction with development partners.

This platform is available with our Microcontroller build W65C165i1 as a base build, however the option to customize the on board build to meet your unique requirements is available by contacting WDC. This agnostic system is flexible to meet all system requirements for development.

WDC FPGA Supported Mods


FPGA vs. ASIC Design Advantages

 FPGA Design
Advantage Benefit
Faster time-to-market No layout, masks or other manufacturing steps are needed
No upfront non-recurring expenses (NRE) Costs typically associated with an ASIC design
Simpler design cycle Due to software that handles much of the routing, placement, and timing
More predictable project cycle Due to elimination of potential re-spins, wafer capacities, etc.
Field reprogramability A new bitstream can be uploaded remotely
ASIC Design
Advantage Benefit
Full custom capability For design since device is manufactured to design specs
Lower unit costs For very high volume designs
Smaller form factor Since device is manufactured to design specs

FPGA vs. ASIC Design Flow

The FPGA design flow eliminates the complex and time-consuming floor planning, place and route, timing analysis, and mask / re-spin stages of the project since the design logic is already synthesized to be placed onto an already verified, characterized FPGA device. However, when needed, WDC provides the advanced floorplanning, hierarchical design, and timing to allow users to maximize performance for the most demanding designs.

Design Flow Outline:


PLD Design Flow

  1. Architecture design. This stage involves analysis of the project requirements, problem decomposition and functional simulation (if applicable). The output of this stage is a document which describes the future device architecture, structural blocks, their functions and interfaces.
  2. HDL design entry. The device is described in a formal hardware description language (HDL). The most common HDLs are VHDL and Verilog.
  3. Test environment design. This stage involves writing of test environments and behavioral models (when applicable). They are later used to ensure that the HDL description of a device is correct.
  4. Behavioral simulation. This is an important stage that checks HDL correctness by comparing outputs of the HDL model and the behavioral model (being put in the same conditions).
  5. Synthesis. This stage involves conversion of an HDL description to a so-called netlist which is basically a formally written digital circuit schematic. Synthesis is performed by a special software called synthesizer. For an HDL code that is correctly written and simulated, synthesis shouldn’t be any problem. However, synthesis can reveal some problems and potential errors that can’t be found using behavioral simulation, so, an FPGA engineer should pay attention to warnings produced by the synthesizer.
  6. Implementation. A synthesizer-generated netlist is mapped onto particular device’s internal structure. The main phase of the implementation stage is place and route or layout, which allocates FPGA resources (such as logic cells and connection wires). Then these configuration data are written to a special file by a program called bitstream generator.
  7. Timing analysis. During the timing analysis special software checks whether the implemented design satisfies timing constraints (such as clock frequency) specified by the user.